Semicon 2.0 Notified: All Six Pillars Launched to Boost India's Chip Ecosystem

The Union government has issued notifications for all six pillars of the Semicon 2.0 scheme, marking a major push to expand India's semiconductor design and manufacturing capabilities. The scheme builds on the earlier Semicon India Programme and offers fiscal and infrastructure support across the entire value chain—from chip design and fabrication to packaging, equipment, materials, R&D, and talent development.

The six pillars cover design, machines and materials, setting up more fabs, strengthening the ATMP/OSAT industry, research and development, and talent development. Together, they span 10 categories, including silicon wafer fabs, compound semiconductor fabs, display fabs, and semiconductor assembly and testing facilities. The scheme will initially accept applications for three years, with projects generally running up to six years.

Addressing the media, Union Minister for Electronics and Information Technology Ashwini Vaishnaw said India achieved its target of developing 85,000 semiconductor engineers in just four years, against a 10-year goal. A new target of training one lakh more engineers has been set. He added that close to 10% of the global semiconductor industry's market is expected to be in India in the coming years.

Students from Tier-II and Tier-III cities have already designed more than 250 chips, the minister noted. In one case, commercial production began within 13 months of groundbreaking, with approvals granted in as little as 90 days in some instances. The ecosystem is expected to create 50,000–60,000 direct jobs.

The India Semiconductor Mission (ISM) will serve as the nodal agency for Semicon 2.0, handling applications, technical and financial appraisal, and implementation oversight. ISM may work with C-DAC for design and deployment categories and plans to announce semiconductor deep-tech awards from 2026. A mid-term assessment will be conducted after three years to evaluate the scheme's impact.